Journals
- R C Panicker, S Puthusserypady and Y Sun, “An Asynchronous P300 BCI with SSVEP Based Control State Detection”, IEEE Tran. Biomed. Eng., vol. 58, no. 6, pp. 1781-88, 2011. [Download]
- R C Panicker, S Puthusserypady and Y Sun, “Adaptation in P300 Brain-Computer Interfaces: A Two-Classifier Co-Training Approach”, IEEE Tran. Biomed. Eng., vol.57, no. 12, pp. 2927-35, 2010. [Download]
- A Kumar, S Fernando and R C Panicker, "Using FPGA as a Platform for Project-based Learning in Embedded Systems Education", IEEE Tran. Education., 2013, Accepted. [Download]
Conferences
- A Kumar, R C Panicker and A Kassim, "Enhancing VHDL Learning through a Light-weight Integrated Environment for Development and Automated Checking", Proc. IEEE Intl. Conf. Teaching, Assessment and Learning for Engineering (TALE), 26-29 Aug 2013, Bali, Indonesia, 2013. [Download]
- K Khurana, P Gupta, R C Panicker and A Kumar, ``Development of an FPGA-Based Real-Time P300 Speller", Proc. Intl. Conf. Field Programmable Logic and Applications (FPL2012), 2012. [Download]
- R C Panicker, S Puthusserypady, A P Pryana and Y Sun, “Asynchronous P300 BCI: SSVEP-Based Control State Detection”, Proc. European. Sig. Pro. Conf. (EUSIPCO-2010), Aalborg, Denmark, Aug 2010. [Download the full paper]
- R C Panicker and S Puthusserypady, “A constrained genetic algorithm for efficient dimensionality reduction for pattern classification”, Proceedings of the 2007 International Conference on Computational Intelligence and Security (CIS2007), Harbin, China, December 2007. (Published by the IEEE, acceptance rate : 17%)