EE4001 Final Year Projects

 

Academic Year 0809

 
 

Project 1:
Optical lithography simulation
Lithography simulation has significant engineering impact. Not only does it provide basic physical understanding, but more importantly, it provides insight and guide innovation. Our objective in this project is to simulate the critical dimension (CD) profile during the lithography process. Existing software such as SAMPLE and Prolith cannot simulate spatial effect of CD along the wafer. One of the aims of this project is to do that.

The software can be developed in Matlab or C. Experimental results will be conducted to validate the model. This is a continuation of last year FYP, initial results are very promising closely matching commercial software. A web-based simulator using Java has also been developed. The student will make use of existing platform to enhancement the system.

A number of interesting features will be added and investigated.
1. Multiple critical dimensions,
2. Spatial effect of CD along the wafer,
3. Effects of heating mechanism, and
4. 3D profiles, etc.

The project is also suitable for student interested in doing a graduate degree.

 
Project 2:
Modeling of multi-zone thermal processing systems in lithography
Temperature control is critical in the processing of silicon wafers with stringent specifications and has a significant impact on the linewidth or critical dimension (CD). The most temperature sensitive step in the lithography sequence is the post-exposure bake step.

In this project, we are interested to develop a dynamic model of the heating process in the lithography sequence that can capture its transient as well as steady-state characteristics. Previous work in the literature are usually steady-state models with a number of limitations.

The student will build the model based on first principle heat transfer (Prerequisite knowledge of heat transfer is not required). Experiment can be conducted to verify the proposed model. In particular, the second half of the project involves making use of this new model for in-situ temperature control, this will be a significant improvement from our earlier work [1].

Reference:
[1]. Tay et al., "Estimation of wafer warpage profile during thermal processing in microlithography", Review of Scientific Instruments, 76(7), 2005.

The project is also suitable for students with interest in graduate studies.

 

  
Project 3:  
Real-time monitoring and control systems in lithography
This is part of an A*Star SERC funded project on "Real-time monitoring and control of CD uniformity in lithography". You will work in a research team consistings of fellow undergreduate students, graduate students, postdocs as well as research engineers from the Singapore Insititute of Manufacturing Technology.

Student 1:
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To implement in-situ CD measurement, we proposed to develop an array of high speed scatterometers. Scatterometry is based on the reconstruction of the grating profile from its optical diffraction responses. A number of configurations exist in the literature. For sub-100 nm feature size measurement, a broadband light source is used to provide the illumination. Each optical path will consist of the broadband light source, two rotating polarizing filters, the wafer, and the spectrometer. During measurement, the analyzer is fixed while the polarizer rotates continuously to create a time-variant signal at the spectrometer. The rotating polarizer technique is optically and mechanically simple. Only polarizers and focusing lenses are used in the light path, and these optical elements are relatively easy to make and characterize. Furthermore, since the analyzer angle is fixed during the measurement, the spectrometer does not need to be insensitive to the polarization of the incidence light.

An initial prototype system has been developed. (Interested students can visit the Advanced Control Technology lab to take a look) The student will now develop on top of the existing system, integrate with a thermal system to demonstrate the idea of real-time control.

Student 2:
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The second task is to analyze the measured data. The extraction of a latent image features can be viewed as an optimization problem. The objective is to find a profile whose simulated diffraction responses match the measured responses. Optimization techniques, such as simulated annealing and gradient based optimization search, have been applied. However, for complicated profiles, it is computationally prohibitive to exhaustively search for the optimal profiles. We proposed here a method based on a combination of rigorous physical modeling of the CD structure and convex optimization. In addition, conventional scatterometry system assume uniform optical property of the line and background materials, we proposed to integrate an array of spectrometers to monitor the optical properties of the materials and feedback into the physical model for real-time optimization. The physical model can thus be developed using rigorous coupled wave analysis to predict the diffraction from a latent image as a function of the wafer optical properties and the photoactive compound (PAC) concentration distribution inside the photoresist.

The student will develop the software for CD extraction using Matlab or C++. The student will first understand the theory of rigorous coupled wave analysis. Integration with the hardware system will be done in the second half of the project. Both projects are also suitable for student interested in graduate studies.

 

  
Project 4:  
Performanced-based optical proximity correction
Optical Proximity Correction (OPC) is an integral part of the Design-to-Manufacturing tape out flow. It is widely adopted in the industry to correct systematic and stable within-field patterning distortions caused by proximity effects, such that to minimize the across-chip linewidth variation. Along the continued shrinking of critical dimension (CD), it was observed that the OPC correction scheme inevitably becomes more aggressive nowadays; and therefore the mask complexity and design turn-around time proportionally increases. This could partly be attributed to the purely geometry-based OPC algorithm which tries to match every edge in the layout, without much consideration of its actual impact on circuit performance. Hence, it is possible that an over-corrected OPC mask would just slightly outperform a moderate-corrected OPC mask but at a much higher cost. Even with an aggressive correction scheme, there is no guarantee that the printed pattern (by the OPC mask, within CD tolerance) will perform closely to the designed performance. Another issue is the escalating mask cost due to an aggressive correction scheme.

In this project, the motivation is to propose an OPC algorithm based on the transistor circuit performance rather than desired mask pattern. The two key performance indexes of transistors, drive current (Ion) and leakage current (Ioff), are chosen to monitor this device performance-based OPC flow. Initial simulation results have been very positive [1].

From the given design layout, the desired performance of transistor will be extracted using SPICE simulation. The mask is initialized to an exact replica of design layout. Mentor Graphics Calibre is used as the lithography process simulator to simulate the printed patterns on wafer.

This project is suitable for students in the control and microelectronics track.

[1] SH Teh, CH Heng and A Tay, 'Design-process Integration for Performance-based OPC Framework', 45th Design Automation Conference, June 2008, CA, USA.

 

  
Project 5:  
Simulation of Integrated Circuit Performance Variability
The constant and aggressive scaling of silicon technology [1] has enabled dramatic improvements in integrated circuit performance. However, as device parameters are scaled, control of semiconductor manufacturing processes has become increasingly difficult, and variability in circuit performance has become more significant. Therefore, the robustness of circuits has emerged as a major road-block in IC design. This project aims to address the issue of manufacturing variations from both a process control perspective and a circuit design perspective through the use of a Monte Carlo simulation framework. The simulation framework includes detailed models of spatial variation of gate length. The Monte Carlo framework will then be used to identify the most effective forms of process control as well as design techniques that mitigate the effects of variations.

No prior knowledge of IC design or advanced control is required. The student will learn about Monte Carlo simulation, IC design, control and optimization. This project is suitable for students in the control and microelectronics track.

[1] International Technology Roadmap for Semiconductors, www.itrs.net

 

  
Project 6:  
Development of a low cost tissue microarrayer
Understanding the basis of tumour development and progression, and identifying biomarkers for assessment of prognosis and prediction of therapy outcome are integral parts of medical research efforts nowadays. This effort is catalyzed with the application of tissue micro arrays (TMA), which represents a high-throughput method for testing biomarkers at a nucleic acid and protein levels, primarily (but not exclusively) in the area of cancer.

A critical analysis of the existing TMA technology, however, indicates that it has serious drawbacks as follows:
1. Expensive for the limited value that it provides (average US $80,000 – 250,000), so that not affordable to all pathology laboratories
2. Non-portable (large footprint), so that its use is geographically restricted
3. Complicated to work with
4. Low accuracy

Therefore, although the technology itself is appealing and tissue data is highly required, the lack of affordable devices and the limitations in the technology used inhibits a widespread application in the pathology laboratories.

These motivation factors induce an opportunity to bridge the gap between a need to accessible TMA resources and the current situation of insufficient access to the said resources. The contribution at sight is a device – instead of a procedure – to enable and assist efficient TMA collection in the most flexible manner.

The student will improve on an existing design, built and test the prototype systems. This is a collaborative project with the medical faculty.

 

  
Project 7:  
Recursive identification of state-space models
The direct identification of state-space models has many advantages over the input-output based identification. Non-recursive batch processing are appropriate for off-line identification. On the other hand, on-line identification of state-space model is more suitable for applications where real-time informations can provide a better fit of the model.

In this project, our objectives are to understand the current approaches to recursive state-space identification and apply it to a thermal processing problem in lithography. In particular, for our application, we required the state-space model to take on certain structures. Simulation will be done to understand the different algorithms. Experiments will be conducted on the actual system to demonstrate the feasibility of the approach.

EE4307 is not a pre-requisite for this project, but will be useful. Simulation will be conducted using Matlab, experiments done using LabView.

 

  
Project 8:  
Estimation of photoresist properties in lithography
Photoresist thickness and extinction coefficient are two important parameters in the microelectronics processing, and these two parameters can be estimated using simple setup of reflectrometry. The literature consists of a number of different techniques for in-situ monitoring of photoresist properties in microlithography process. These monitoring methods usually work under the assumption that the inspected wafer is flat.

In this project, our objective is to investigate how these measurements and estimations are affected for warped wafers. First, wafer warpage is common in microelectronics processing. Warpage can affect device performance, reliability and linewidth or critical dimension (CD) control in various microlithographic patterning steps. Warped wafers also affect the various baking steps in the microlithography sequence. Current techniques for measuring wafer warpage are mainly off-line methods where the wafer have to be removed from the processing equipment. We have previously proposed an in-situ methods for detecting wafer warpage.

This work is motivated by the fact that almost all wafers are warped in one form or another due to mechanical as well as thermal stress induced during processing. The ability to detect wafer warpage in-situ during processing would be invaluable. A novel technique of using conventional reflectometer to conduct in-situ wafer warpage detection is proposed.

Experiments will be conducted. This project does not require prior understanding of the wafer fabrication process.

 

  
Project 9:  
Low temperature microwave heating for photoresist processing
In the semiconductor industry, resistance heaters (IR heating) are used as the heat source for curing of films on semiconductor wafers used in IC processing. The introduction of new materials (e.g. NiSi) has driven the need for new technical requirements, which include: 400°C maximum temperature operation, ppb wafer ambient control, and most significant uniform temperature gradients across all wafers in the batch.

Although industrial applications have used microwave for decades, microwave heating of silicon hasn't been possible due to difficulties in power density control (hot spots), effective depth of penetration, and cost control. Low temperature microwave heating is a promising candidate for these applications. The possibility of heating the silicon wafers in a batch at fast ramp rates while minimizing the delta temperature gradient across the wafer is exciting

Some of the features of microwave heating includes volumetric heating throughout the material. Microwave energy can also effectively couple with O-H bonds in the films, which dramatically reduces the moisture content, which is not possible with conventional heating. These systems can potentially also reduces curing temperatures, lowers operational costs, improves film quality, and dramatically improves cycle time.

The student will survey microwave heating technology, simulate and analyse the potential benefits of using microwave heating for photoresist processing in lithography. Simulation will be done in Matlab.