Dept of Electrical and Computer Engineering

| Autobiography | Research |

Li Ming Fu

Professor

Dipl Fudan  

E-mail: elelimf@nus.edu.sg Phone:(65)6874 2559 Fax:(65)6779 1103

Professional Working Experience

M.F. Li graduated from the Department of Physics, Fudan University , Shanghai . After graduation, he joined the Department of Applied Physics, University of Science and Technology of China (USTC) as a teaching assistant and then a lecturer . He joined the Graduate School , Chinese Academy of Sciences, Beijing in 1978 and became a Professor in 1986 . He has also served as Adjunct Professor at the Institute of Semiconductors/Chinese Academy of Sciences, Fudan University, and USTC, Hefei, China .

 

He was a visiting scholar  at Case Western Reserve University, OH in 1979; the University of Illinois, Urbana-Champain from1979 to 1981, under the guidance of Professor C.T.Sah; and was a visiting scientist at the University of California , Berkeley and Lawrence Berkeley National Laboratories from 1986 to 1987, and 1990 to 1991 . He joined the National University of Singapore in 1991 , where he is  a Professor in the Electrical and Computer Engineering Department . Since 2003, he is also a senior member technical staff at the Institute of Microelectronics, Singapore. He has published over 300 research  papers, and two books, including " Modern Semiconductor Quantum Physics" (World Scientific in 1994 ). He has served on several international program committees and advisory committees in semiconductor conferences in Canada, China, Germany, Japan, Singapore, Taiwan China and USA .

 

 

Research Interests :

 

Nano-CMOS Electron Devices : 

 

Si Technology : High-k/metal gate stack, Schottky S/D transistors , high mobility channel materials , novel device structures

 

Device Reliability Physics

 

Quantum modeling and simulation

 

 

 

 

Research Projects

 

Research Projects conducted in Li’s group covers very wide scope including  Si technology , device reliability , and physical modeling and simulation. However, all research topics are focused on nano-CMOS devices. We presently have the following research projects:

 

High k gate dielectric/metal gate:  Because of the high tunneling current, SiO2 will be no longer suitable for gate dielectric when the CMOS transistors are scaled down to nano regime with the effective gate oxide thickness (EOT) of 1nm or less. High k dielectric with thicker physical thickness and therefore lower tunneling current will replace SiO2 as gate dielectric in the future generation MOSFETs.  HfO2 has emerged as one of the most promising high-K gate dielectrics to replace SiO2 due to its high dielectric constant, moderate energy gap and electron and hole barriers to Si. However, HfO2 has some serious problems such as low crystallization temperature, channel mobility degradation, threshold voltage instability etc. Our research is focused on new HfO2 based dielectric materials and technology to overcome these problems and further reduce the EOT to sub-0.6 nm , without sacrifice the electric performance of MOSFETs .  Metal gate will be used to replace poly-Si as gate electrode in the future generation CMOS transistors. Poly-Si gate has the following problems:  Poly-depletion, Boron penetration, gate resistance, work function not fit to the requirement of ultra-thin body Si-on-Insulator (SOI) transistors. Our research on metal gate is focused on new metal gate materials and technology to fit the requirement of the metal work function for nano-CMOS transistors, with high thermal stability. We have developed the first HfN/SiO2 and HfN/HfO2 gate stack technology, using the high thermal stability and oxygen resistance of the HfN metal gate ( publications 1,5,8,9,11) , reaching 0.8nm EOT of HfN/interfacial layer , without surface nitridation, so good channel mobility and low interface trap density have been achieved. When using surface nitridation, EOT is further reduced to 0.6nm.

 

Our research team have close collaboration with other professors within the Silicon Nano Device Lab  (SNDL), ( see SNDL web : http://www.ece.nus.edu.sg/sndl/ ) focusing on the research of high-k high density Metal-Insulator-Metal (MIM) capacitors, and its applications in Analog and RF Integrated circuits (Publications 19-24).

 

Nano CMOS device reliability Physics: When the CMOS device scaled to nano regime, the electric field in the device becomes very high.  A lot of reliability issues becomes crucial. The most serious problems are: (1). Bias Temperature Instability (BTI) due to charge trapping in the gate dielectric and the interface traps, giving rise the threshold voltage shift of the MOS transistors. We are the first to point out the importance of dynamic BTI effect in real transistor application , and the recovery of interface trap degradation in the passivation phase under dynamic stress (publications 26,30,36) . The dynamic BTI degradation is much lower than the static BTI due to passivation effect in the dynamic stress. (2). Gate dielectric integrity including breakdown, quasi-breakdown (soft-breakdown), and stress induced leakage current (SILC), particularly the new issues and new degradation mechanism in high-k dielectric/interfacial layers.  Our research is focused on the physical understanding of device reliability issues, and technical improvement by choosing new materials and technology and operation mode.  

 

 

Metal –Semiconductor Schottky contact and its application in CMOS transistors: Schottky contact has high potential in semiconductor devices , particularly its potential in nano CMOS transistors to replace conventional pn junction source and drain . The Schottky barrier Source/Drain Transistor (SSDT) architecture has been proposed to overcome the series resistance problem of ultra-shallow source/drain (s/d) junction of sub-50nm MOSFETs, due to the abrupt silicide/Si interface and low resistance of silicide. The barrier height of the Schottky junction should be as low as possible to obtain high driving current and to prevent two different slopes in the subthreshold region of the MOSFETs. SSDT is particularly attractive for metal gate/high-K gate stack as it avoids the use of high temperature annealing process required for implanted S/D, hence eliminating the thermal stability issues associated with high-K/metal gate stack. The most difficult problem of SSDT is to make n-MOSFET with good performance comparable to the conventional n-MOSFET  performance . The key is to reduce the electron barrier of the Schottky contact . We have made some very encouraging progress by using Dy and Yb Silicide to improve the surface morphology and to reduce the electron barrier of the Schottky contact.( Publications 2,3 )

 

Quantum modeling and simulation of nano CMOS devices and  investigation of CMOS compatible emerging devices for the future integrated circuit applications :

 

When the CMOS device scaled down to the nano regime, quantum effects become very important.   Manifestation of quantum effects include: the carrier quantization effect due to quantum confinement in nano width channel in the inversion layer ( publications 48,54,56 )or ultrathin body (UTB) in Si-on-Insulator (SOI) ( Publications 44,45,46,51); quantum tunneling or resonant tunneling effect through the nano width barrier( Publications 47,49,52,53,55); inelastic tunneling and charge trapping with interaction with lattice phonon or lattice distortion ( publication 28) ; atomistic simulation, beyond the effective mass envelop function approximation for the band structure and carrier wave functions , for future nano devices, etc . We have a small however high quality team and we need students with strong background in Physics, with strong interests and enthusiasm, dedicating to longer-term research in future nano-CMOS devices.

 

 

Selected Patents

(1) Y.H.Zhang, M.F.Li, S.P.Zhao,G.TT.Sheng and Andrew Yen, " Method and Apparatus for determining characteristics of microstructures utilising micro-modulation reflectance spectrometry ". US patent ( IME ) 1997 .

 

(2) M.F.Li, Uday Dasgupta, Y.C.Lim, " A rail-to-rail low voltage operational transconductance amplifier ", Singapore Patent ( NUS), 1997.

 

(3)H.Y.Yu, M.F.Li, K.Bera, D.L.Kwong , “A THERMAL ROBUST SEMICONDUCTOR DEVICE USING HFN AS METAL GATE ELECTRODE AND THE MANUFACTURING PROCESS THEREOF”, US patent ( NUS/IME), 2003

 

(4) M.F.Li, Jagar Singh, Y.T.Hou, N. Balasubramanian and Lin Fujiang , “CMOS Compatible Low Band Offset Double Barrier Resonant Tunneling Diode”, US Patent (IME),2003

 

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Selected Recent Publications

 

Click blue underlined paper title to read and download the paper

I.                   Journal and Conference papers

 

High-k/Metal Gate/Schottky Contact

 

 1. H.Y.Yu, J.F.Kang,C.Ren,J.D.Chen, Y.T.Hou, C.Shen, M.F.Li, DSH Chan KL Bera , CH Tung, DL Kwong, “Robust high-quality HfN-HfO2 gate stack for advanced MOS device application, IEEE Electron Device Letts, v.25, no.2, pp.70-72(2004).

 

2. S.Y.Zhu, H.Y.Yu, S.J.Whang, J.H.Chen, C.Shen, C.Zhu, S.J.Lee, M.F.Li, DSH Chan, WJ Yoo, A.Du, C.H.Tung, Jagar Singh, Albert Chin, D.L.Kwong, “Schottky-Barrier s/d MOSFETs with high-k gate dielectrics and metal-gate electrode”, IEEE Electron Device Letts , v.25, no.5, pp.268-270(2004).

 

3. S.Y.Zhu, J.Chen, M.F.Li, S.J.Lee, J.Singh, C.X.Zhu, A.Du, C.H.Tung, C.H.Tung, Albert Chin, D.L.Kwong, “N-Type Schottky-Barrier s/d MOSFETs using Ytterbium Silicide”, IEEE Electron Device Letts , v.25, no.8, pp.565-657(2004).

 

4. H.Y.Yu, Chi Ren, Yee Chia Yeo, J.F.Kang, X.P.Wang, H.H.H.Ma, M.F.Li, DSH Chan, D.L.Kwong,”Fermi Pinning induced thermal instability of metal gate work functions”, IEEE Electron Device letts, v.25, n.5, pp.337-339 (2004)

 

5. H.Y.Yu, M.F.Li and D.L.Kwong , “Thermally robust HfN metal as a promising gate electrode for advanced MOS devices applications”, IEEE. Trans. Electron Devices, v.51,n.4,pp.609-615(2004) .

 

6. Xiongfei Yu,  Chunxiang Zhu, X.P. Wang, M.F. Li, Albert Chin, A. Du, W.D. Wang, Dim-Lee Kwong , “High Mobility and Excellent Electrical Stability of NMOSFETs Using a Novel HfTaO Gate Dielectrics” , Symposium VLSI  Tech, Hawaii, 2004

 

7. M.F.Li, H.Y.Yu, Y.T.Hou, J.F.Kang, X.P.Wang, C.Shen, C.Ren, Y.C.Yeo, C.X.Zhu, DSH. Chan , A.Chin, D.L.Kwong, “Selected Topics on HfO2 Gate Dielectrics for Future ULSI CMOS Devices” , ( invited) ICSICT2004, Beijing .

 

8. HY. Yu,  HF.Lim, JH Chen, MF Li, CX Zhu, CH. Tung, AY Du, WD Wang, DZ Chi and DL Kwong, “ Physical and electrical characteristics of HfN gate electrode for advanced MOS devices “   IEEE Electron Device Letts , v.24,n.4, p.230-232 ,( 2003) .

9. H.Y. Yu, H.F. Lim, J.H. Chen, M.F. Li, C.X. Zhu, D.-L. Kwong#, C.H. Tung*, K.L. Bera*, and C.J. Leo*,  “Robust HfN Metal Gate Electrode for Advanced MOS Devices Application”, Symposium VLSI Technology , Kyoto,2003 . 

10.C. H. Huang, M. Y. Yang, Albert Chin, W. J. Chen, C. X. Zhu, B. J. Cho, M.-F Li, and D. L. Kwong , “Very Low Defects and High Performance Ge-On-Insulator p-MOSFETs with Al2O3 Gate Dielectrics”, Symposium VLSI Technology, 2003, Kyoto.

 

11.H.Y.Yu, J.F.Kang, J.D.Chen, C.Ren, Y.T.Hou, M.F.Li, DSH Chan, D.L.Kwong, K.L.Bera , C.H.Tung, “Thermally Robust High Quality HfN/HfO2 Gate Stack for Advanced CMOS Devices” , International Electron Device Meeting (IEDM) 2003,Tech Digest, p.99-102.

 

12. C.H.Huang,D.S.Yu,Albert Chin,C.H.Wu,W.J.Chen ,C.X.Zhu, M.F.Li, B.J.Cho and D.L.Kwong,”Fully Silicide NiSi and Ge NiGe Dual Gates on SiO2/Si and  Al2O3/GOI MOSFETs” IEDM 2003, Tech Digest, pp.319-322.

 

13.Nan Wu, Qingchun, Chunxiang Zhu, M.F.Li, DSH Chanh, Albert Chin, D.L.Kwong ,L.K.Bera, N.Balasubramanian, A.Y.Du, C.H.Tung, Haitao Liu, Johnny K.O.Sin , “ Ge pMOSFETs with MOCVD HfO2 gate dielectric”, 2003 Int. Semiconductor Device Research Symposium, Symposium Proceeding , pp.252-253.

14.Qingchun Zhang, Nan Wu, Chunxiang Zhu, M.F.Li, DSH Chan, Albert Chin, D.L.Kwong, L.K.Bera, N. Balasubramanian, A.Y.Du, C.H.Tung, Haitao, Johnny Sin, “Germanium pMOSFET with HfON Gate Dielectric”, 2003 Int. Semiconductor Device Research Symposium, Symposium Proceeding , pp.256-257.

 

15.H.Y. Yu, N. Wu, M.F. Li, C.X. Zhu, B.J.Cho,D.L.Kwong, C.H. Tung, J.S. Pan, J.W. Chai, W.D Wang D.Z. Chi, S. Ramanathan , "Thermal stability of (HfO2)x(Al2O3)1-x on (100) Si", Appl. Phys. Lett. vol. 81, pp. 3618-3620, 2002

 

16.H.Y. Yu,M.F. Li, B.J.Cho,C.C. Yeo, M.S. Joo, D.L.Kwong,J.S.Pan,C.H. Ang,J.Z.Zheng, S.Ramanathan , "Enery Gap and band Alignment for (HfO2)x(Al2O3)1-x on (100) Si",Appl Phys. Lett,' vol 81,pp. 376-378, 2002

 

17.H.Y.Yu,Y.T. Hou,M.F.Li and D.L.Kwong , "Investigation of Hole Tunneling Current through Ultrathin Oxynitride/Oxide Stack Gate Dielectrics in p-MOSFET's ",IEEE Trans. Electron Devices, vol.49, pp.1158-1164, 2002

 

18.H.Y.Yu,Y.T. Hou,M.F.Li and D.L.Kwong , Hole Tunneling Current through Oxynitride/Oxide Stack and the Stack optimization for p-MOSFET's ",IEEE Electron Device Letters, vol.23, pp.285-287, 2002

 

 

MIM Capacitors

 

19.Sun Jung Kim, Byung Jin Cho, S. J. Ding, M.-F. Li, M. B. Yu, C. Zhu, A. Chin, and D.-L. Kwong “Engineering of Voltage Nonlinearity in High-K MIM Capacitor for Analog/Mixed-Signal ICs” Symposium VLSI  Tech , Hawaii (2004).

 

20.S.J.Ding, H.Hu, H.F.Lim, S.J.Kim, X.F.Yu, C.Zhu, M.F.Li, B.J.Cho, DSH Chan, S.C.Rustagi, A.Cghin, DL Kwong ,”High-Performance MIM Capacitor using ALD high-k HfO2-Al2O3 laminate dielectrics”, IEEE Electron Device Letts, v.24,n.12, pp.730-732 (2003)

 

21.S.J.Kim, B.J.Cho, M.F.Li, X.F.Yu, C.Zhu, A.Chin, D.L.Kwong,”PVD HfO2 for high-precision MIM capacitor applications”, IEEE Electron Device Letts, v.24,n.6, pp.387-389 (2003)

 

22.X.F. Yu, C. Zhu, Hang Hu, Albert Chin, MF Li, Byung Jin Cho, Dim-Lee Kwong , P. D. Foo, Ming Bin Yu , “A High Density MIM Capacitor (13 fF/μm2) Using ALD HfO2 Dielectrics” ,  IEEE Electron Device Letts, v.24,n.2, pp.63-65 ( 2003).

 

23.S.J. Kim, Byung Jin Cho, Ming-Fu Li, Chunxiang Zhu, Albert China, and Dim-

Lee Kwongb , “HfO2 and Lanthanide-doped HfO2 MIM Capacitors for RF/Mixed IC Applications”, Symposium VLSI Technology , 2003,   Kyoto. Pp.77-78.

 

24.H.Hu, S.J.Ding,H.F.Lim, C.X.Zhu, M.F.Li, S.J.Kim, X.F.Yu,J.H.Chen, Y.F.Yong, B.J.Cho ,DSH Chan, Subhash C Rustagi, M.B.Yu, A.Du, D.My, P.D.Fu, Albert Chin, D.L.Kwong, “High Performance ALD HfO2-Al2O3 Laminate MIM Capacitors for RF and Mixed Signal IC Applications”  IEDM 2003, Tech Digest, p.379.

 

CMOS  Device Reliability

 

25.M.F.Li , D.L.Kwong ,” Dynamic BTI in Ultrathin SiO2 and HfO2 MOSFETs and its impact on device lifetime”, IWDTF2004 ( International workshop on dielectric thin films for future ULSI devices-science and technology, Tokyo, May 2004 (Invited)

26.M.F.Li, G.Chen, C.Shen, X.P.Wang, H.Y.Yu, Y.C.Yeo, D.L.Kwong, “Dynamic Bias-Temperature Instability in Ultrathin SiO=2 and HfO2 Metal-Oxide-Semiconductor Field Effect Transistors and its Impact on Device Lifetime”, Jp.JAP , v.43,n.11B. (2004)

27.Shen Chen, H.Y.Yu, X.P.Wang, M.F.Li, Y.C.Yeo, DSH. Chan, KL Bera, DL Kwong ,”Frequency dependent dynamic charge trapping in HfO2 and threshold voltage instability in MOSFETs “ International Reliability Physics Symposium (IRPS) 2004, p. 601. Phoenix,2004 

 

28.Shen Chen , M.F.Li, X.P.Wang, H.Y.Yu, Y.P.Feng, ATL Lim, Y.C.Yeo, DSH Chan , D.L.Kwong “Negative U Traps in HfO2 Gate Dielectrics and Frequency Dependence of Dynamic BTI in MOSFETs” , IEDM 2004, Tech Digest, p.733.

 

29.W. Y. Loh, B J Cho, M F Li, Daniel S H Chan, C H Ang, J Z Zhen and D L Kwong, “Localized Oxide Degradation in Ultra-Thin Gate Dielectric and its Statistical Analysis”,  IEEE Tran. ED , 50,n.4,pp.967-972 (2003)

 

30.G.Chen, K.Y.Chuah, M.F.Li, DSH Chan, C.H.Ang, J.Z.Zheng, Y. Jin and D.L.Kwong , “Dynamic NBTI of pMOS transistors and its impact on MOSFET lifetime”, 2003 IEEE Int. Reliability Physics Symposium (IRPS) , Dallas, pp.196-202,(2003)

 

31.M.F.Li, B.J.Cho,G.Chen, W.Y.Loh and D.L.Kwong , New Reliability Issues of CMOS transistors with 1.3nm thick gate oxide, ( invited) , Seventh International Symp on Silicon Nitride and Silicon Dioxide thin insulating films, Electrochemical Society , Paris , 2003.

 

32.W.Y.Loh,B.J.Cho,M.S.Joo,M.F.Li and D.L.Kwong,”Analysis of Charge Trapping and Breakdown mechanism in High-K Dielectric with Metal Gate Electrode using Carrier Separation” IEDM 2003,Tech Digest, p.927-930.

 

33.W Y Loh, B J Cho and M F Li, "Evolution of Quasi-breakdown in Thin Gate Oxides", J. Appl Phys., vol 91,no.8,p.5302-5306,2002

 

34.W Y Loh, B J Cho and M F Li, "Correlation between interface traps and gate oxide leakage current in the direct tunneling regime", Appl Phys. Lett., vol 81,no.2,p.379-381,2002

 

35.G.Chen,M.F.Li,Y.Jin, "Interaction of interface-traps located at various sites in MOSFETs under stress", IEEE Trans. Reliability, Vol. 51, no.4,pp.387-391,2002

 

36.G.Chen,M.F.Li,C.H.Ang,J.z.Zhen and D.L.Kwong, "Dynamic NBTI of pMOS Transistors and its impact on MOSFET scaling", IEEE Electron Device Letts., vol. 23,n.12, pp.734-736 (2002)

 

37.B.B.Jie , W.K.Chim, M.F.Li, and K.F.Lo , " Analysis of the DCIV peaks in electrically-stressed pMOSFET's " IEEE Trans. ED , vol. 48 , p.913 (2001)

 

38.Chen Gang , M.F.Li and X.Yu , " Interface traps at high doping drain extension region in sub-0.25 um MOSTs " IEEE EDL , vol. 22, p.233 ,(2001)

 

39.H. Guan , B.J.Cho, M.F.Li,Z.Xu , Y.D.Ho and Z.Dong , " Experimental evidence of interface-controlled mechanism of quasi-breakdown in ultra-thin gate oxide " IEEE Trans. ED , vol.48 , p.1010, (2001)

 

40.S,G,Ma , Y.H.Zhang, M.F.Li, W.D.Li, J. Xie, GTT. Sheng, A.C.Yen and JLF Wang , " Gate-Induced Drain Leakage Current Enhanced by Plasma Charging Damage ", IEEE Trans., Electron Devices , vol. 48, p.1006 (2001)

 

41.G. Chen , M.F.Li and Y.Jin , Electrical passivation of interface traps at drain junction space charge region in p-MOS transistors , Proceeding 12th ESREF , 1-5, Oct ,2001 , Bordeaux ,( France) , paper B12, (2001).

 

42.M.F.Li , " Selected Topics in CMOS Transistor Reliability " ( invited ) , 4th SRC-SEMATECH Topical Research Conference on Reliability , Stanford University , CA , Oct.30-Nov.1 , 2000 .

 

43.H.Guan, M.F.Li, Y.D.He, B.J.Cho and Z.Dong, " A Thorough Study of Quasi-Breakdown Phenomenon of Thin Gate Oxide in Duel-Gate CMOSFET's ", IEEE transactions on Electron Devices, vol 47, no. 8, p.1608, (2000). 

 

Nano Device Quantum Modeling and Simulation

 

44.Tony Low, M.F.Li, W.J.Fan, S.T.Ng, Y.C.Yeo, C.Zhu, A.Chin ,L.Chan, D.L.Kwong,” Imapact of Surface Roughness on Si and Ge Ultra-thin-Body MOSFETs”, IEDM 2004 Tech Digest ,p.151.

 

45.Tony Low, Chen Shen, M.F.Li, Y.C.Yeo, Y.T.Hou, C.Zhu, A.Chin, L.Chan, D.L.Kwong

“Study of Mobility in Starined Si and Ge Ultra-thin-Body MOSFETs”, SSDM, Tokyo, p.776 (2004)

 

46.Tony Low, M.F.Li, C.Shen, Y.C.Yeo, Y.T.Hou, C.Zhu, A.Chin, D.L.Kwong,"Electron mobility in Ge and strained-Si channel ultra-thin-body MOSFETs", Appl. Phys. Letts 2004

 

47.Y.T.Hou, M.F.Li, T.Low and D.L.Kwong, ”Metal Gate Workfunction Engineering on Gate Leakage of MOSFETs”, IEEE Trans. Electron Devices, v.51, n.11, pp.1783-1789(2004).

 

48.Tony Low , Y.T.Hou, M.F.Li and Dim-Lee Kwong “Improved one-band self-consistent effective mass methods for hole quantization in p-MOSFET”, IEEE Trans. ED , v.50, n.5, pp.1284-1289 (2003) .

 

49.Y.T. Hou, M.F. Li, D.L. Kwong, “Modeling of Tunneling currents through HfO2 and HfAlO gate stacks and their scalability in CMOS technology, IEEE Electron Device Lett.v.24,n.2,pp.96-98 (2003).

50.Tony Low, Y. T. Hou, M. F. Li, Chunxiang Zhu , D. -L. Kwong# , and Albert Chin, “Germanium MOS: An Evaluation from Carrier Quantization and Tunneling Current”

VLSI Technology Symposium ,2003, Kyoto .

 

51.Tony Low, Y.T.Hou, M.F.Li, C.X.Zhu, Albert Chin , G.Samudra and D.L.Kwong, “Investigation of performance limits of Ge double-gated  MOSFETs”  IEDM 2003, Tech Digest , p.691-694.

 

52.Y.T. Hou, M.F. Li, Y.Jin and W.H. Lai , Direct tunneling Hole Current through Ultrathin Gate Oxides in Metal-Oxide-Semiconductor Devices, J. Appl Phys. , Vol.91, pp. 258-264, 2002

 

53.Y.T. Hou, M.F. Li, D.L. Kwong, Quantum Tunneling and Scalability of HfO2 and HfAlO Gate Stacks, in Tech Digest International Electron Device Meeting (IEDM), San Francisco, CA, pp.731-734, 2002.

 

54.Y.T.Hou and M.F.Li , “ Hole quantization effects and threshold voltage shift in pMOSFET-Assessed by improved one-band effective mass approximation “, IEEE Trans. ED. Vol.48 ,pp.1188-1193, (2001)

 

55.Y.T.Hou ,M.F.Li,,W.H.Lai and Y.Jin , “ Modeling and Characterization of Direct Tunneling Hole Current through Ultrathin Gate Oxide in p-metal-oxide-semiconductor field-effect transistors “ , Appl. Phys. Lett. 78, pp.4034-4036, (2001)

 

56.Y.T.Hou , M.F.Li , “ A simple and efficient model for quantization effects of hole inversion layers in MOS devices “ , IEEE Trans. ED, vol.48, pp.2893-2898, (2001).

 

57.Y.T.Hou , M.F.Li and Y.Jin, Hole quantization and hole direct tunnelling in deep submicron p-MOSFETs , 6th ICSICT 2001 , Shanghai (China ), ( invited ) ,pp. 895-900(2001).

 

 

Others

 

58.C.Y.Lin, A.Chin, Y.T.Hou, M.F.Li, S.P.McAllister and D.L.Kwong, “Light emission near 1.3 um using ITO-Al2O3-Si0.3Ge0.7-Si tunnel diodes”, IEEE Photonics Technology Lett. Vol.16, no.1, pp.36-38 (2004).

 

59.Luo Zhenying, M.F Li, Yong Lian and S.C.Rustagi CMOS TRANSCONDUCTOR DESIGN FOR VHF FILTERING APPLICATIONS , Proceedings of the 2003 IEEE ISCAS , May ,2003, Bangkok , Thailand .

 

60.A.M.Xu , M.F.Li, A 1.2V Rail-to-rail differential mode input linear CMOS transconductor , Proceedings of the 2002 IEEE ISCAS , May ,2002, Phoenix , Arizona

 

61. Y.J.Ha , M.F.Li and A.Q.Liu , " A new CMOS buffer amplifier design used in low voltage MEMS interface circuits " Analog Integrated Circuits and Signal Processing ", vol. 27 , 5 (2001)

 

62.M.F.Li, Uday Dasgupta, X.W.Zhang and Y.C.Lim, " A low-voltage CMOS OTA with rail-to-rail differential input range " IEEE Trans. Circuits and Systems - I ,47, Jan (2000). 

 

 

II. Books and Chapters in Books

 

M.F.Li and P.Y.Yu, " High pressure study of DX centers using capacitance techniques " in " High Pressure in Semiconductor Physics I ", ( invited review article ) Semiconductors and Semimetals, Vol. 54, eds T.Suski and W. Paul, (Academic Press, San Diego), 1998. 

 

Ming-Fu Li, Modern Semiconductor Quantum Physics, International Series on Advances in Solid State Electronics and Technology, Founding Editor : Chih-Tang Sah. ( World Scientific, Singapore.) 1994. 

 

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