Top Surface Aluminized & Nitrided HfAlO/ HfO2 Stack [2004]
  MOSFET with HfTaO Gate Dielectric [2004]
  Substituted Al for Replacement of PolySi Gate [2004]
  PtxSi Replacing PolySi Gate for pMOSFET [2004]
  Work Function Tuning of TaN by Incorporating Lanthanide [2004]
  Development of Metal Gate/ High-k Gate Stacks Etching Process [2004]
  Low Temperature Plasma Nitridation for Removal of Hf-based High-k Gate Dielectrics [2004]
  Plasma PH3 Passivation TaN/ HfO2/ Ge-sub Stack [2004]
  A New Surface Passivation for Ge pMOSFET with HfO2 Gate Dielectric [2004]
  Negative-U Traps in HfO2 Gate Dielectrics and Frequency Dependency of Dynamic BTI in MOSFETs [2004]
  Surface Roughness and UTB MOSFETs Design [2004]
  Enhanced Performance in 50nm N-MOSFETS [2004]
  Fin Tapering Optimization & Fabrication [2004]
  Advanced Process for Dual Metal Gate CMOS [2004]
  Germanium MOSFETs with high-K dielectrics - for high mobility transistors [2004]
  Ballistic Current in Double Gate Ultra-thin Body Ge Transistors  [2004]
  Dynamic NBTI of P-MOSFET in CMOS inverter  [2004]
  High-K MIM Capacitors [2003-2004]
  High-K Quantum Dots Flash Memory Devices [2003-2004]
 

Strained-Channel Transistor Strain Engineering to Improve Speed [2004-2005]

   
   
  SNDL is developing scientific and technological bases for solving the most critical needs for CMOS front-end technology, RF-IC process, and nano technology.

 
  Front-End Technology Research - focusing on 50 nm CMOS and beyond
 



High-K gate dielectrics
Dual-metal gate electrodes
Gate stack etching
New junction technology
High mobility materials
New Device structures
Modeling, simulation, reliability
GOAL: Develop a scientific and technological base for solving the most critical needs for front-end technology that are required for sub-50 nm CMOS transistors
 
 
  On-Chip High-K MIM Capacitors for RF ICs
 
 
 

Research Focus
►Develop low temp high-K MIM process ►compatible with Cu/low-K BEOL
►Modeling and circuit design for Analog/RF ICs
 
 
  Quantum Dots (QD) High-K Flash Memory
 



 


Advantages
Low Power
High Speed
Long Data Retention
High Density
Scalable Tunnel Oxide Thickness
 
 
    New Projects in 2005
  Development of high mobility channel layer formation technology for high speed CMOS devices
 
    New Projects in 2004
  Nanoscale Transistors with Enhanced Performance for CMOS Manufacturing
  Development of Semiconductor Nanowire CMOSFET for sub-45nm technologySi/Ge Nanowire FET with High-K Gate Dielectrics and Metal Electrode
  Non-volatile Molecular and Polymer Memory for Flash Memory in Silicon IC Applications
 

Physical Modeling and Simulation of Nano-Scale Electronic Device Phenomena