Yung Fu Chong's research interests are related to electronic materials and semiconductor devices, with focus on the front-end processing of complementary metal-oxide-semiconductor (CMOS) devices. He has conducted research on the fabrication of ultra shallow p+/n junctions and self-aligned silicides using the laser thermal processing (LTP).

Laser Thermal Processing of ultra shallow junctions typically involves the permorphization of the silicon surface, followed by the melting of the amorphized regions (and the substrate) using a pulsed excimer laser. The extent of dopant diffusion is primarily controlled by the melt depth and due to the near-zero thermal budget of the LTP; an extremely high degree of dopant activation is achieved upon recrystallization. In the formation of ultra shallow junctions, he has also addressed the issue on the transient enhanced diffusion (TED) of boron during a post- LTP rapid thermal anneal. His research on the LTP of ultra shallow junctions requires a sound knowledge of the fundamentals of laser -solid interactions, as well as the defect formation and annihilation process during thermal annealing.

Another area of his research relates to alternative gate activation technologies, their process integration issues and impact on the depletion of carriers at the polycrystalline silicon (poly-Si) gate/gate dielectric interface (poly-depletion). it is known that the poly- depletion effect increases the effective electrical thickness of the gate dielectric and results in drive current degradation. he has recently reported the study on the reduction of poly-depletion in sub-0.1 micro m CMOS devices with the use of advanced gate structures and laser thermal processing. This is a continuation of the work that he carried out at Agere Systems, USA (formerly Bell Laboratories, Lucent Technologies), where he spent nearly one year (in 2001) as a visiting scholar. He has successfully developed a process flow (which involves LTP) to form highly doped poly-Si gated MOS devices with ultra thin gate dielectrics. It is found that the poly-depletion effect in these devices is substantially reduced after subjecting the wafers to laser irradiation, and that the gate oxide reliability is not degraded even after LTP at high fluencies. This process flow is applicable to both PMOS and NMOS devices (with boron and arsenic-implanted gates, respectively) ; hence it is compatiable with the dual-doped gate process in the fabrication of advanced CMOS devices.

He has authored or co-authored more than 10 internatinally reviewed journals and conference proceedings. He has 5 United States Patents, with several more pending. In 2002, he recieved the University Graduate Fellowship award from the National University of Singapore for his outstanding research and academic results. Recently, he delivered a technical presentation at IMEC, Belgium.