TOPIC Beyond-Si to Beyond-CMOS: Perspectives on Logic Nano-electronics Scaling for the next 10 years 
AREA Microelectronic Technologies & Devices  
SPEAKER Dr Aaron Thean, IMEC, Belgium 
DATE 13 April 2015, Monday 
TIME 2:00 pm to 3:00 pm 
VENUE E5-03-19, Engineering Blk E5, Faculty of Engineering, NUS 
FEES No Charge 

A new information super-structure is emerging as we move into the era of Internet of Everything (IoE). With the orders of magnitude increase in connected devices, future networks are expected to evolve differently from today’s internet. As our information infrastructure evolves through the next decade, data centers, smart mobile devices, and sensor nodes will demand a variety of energy-efficient electronic systems that can satisfy a myriad of performance, form-factor, and cost needs. Thus, giving rise to new and mounting challenges for performance, power, cost, and density scaling for nano-electronics. On the other hand, overcoming these new challenges will bring exciting innovations in process capability, material integration, device architectures, and system design. In this talk, we will examine some of the current logic scaling trends, review what are the possible paths forward for process technologies and how they will have to couple closely to new system strategies. I will walk through some of IMEC’s on-going advanced Logic R&D activities and innovations targeting 10nm, 7nm, 5nm, and beyond. This will include the processes for multi-gate devices beyond FinFETs, beyond-Si channel devices, and other emerging Beyond-CMOS device-circuit architectures.


Dr. Aaron Thean is the Vice President of Logic Process Technologies and Director of the Logic Devices Research consortium at IMEC, Belgium. Since moving to Belgium and joining IMEC in 2011, he directs nano-electronic device and process R&D ranging from ultra-scaled transistors, to III-V/Ge heterogeneous integration, emerging device architectures like 2-D crystals and spin logic devices. Prior to joining IMEC, Aaron had held technology management positions at Qualcomm (California, USA) and IBM (New York, USA). As the Manager of Strategic Silicon Technologies at Qualcomm, he was responsible for process-design co-optimization for Qualcomm’s next-generation products, where he worked closely with process and design teams on 20nm technology. At IBM, he led the international R&D alliance team, as the 32nm/28nm manager, to develop and qualify the first foundry-compatible Gate-First High-k Metal Gate bulk CMOS process for IBM and its technology partners. Aaron started his career at Motorola’s Advanced Product Research Development Laboratory – Austin, Texas, where he became the manager of the Novel Devices Group. An alumni of the University of Illinois at Champaign-Urbana USA, he received his B.Sc (Highest Honors), M.Sc, and Ph.D (2001) degrees in Electrical Engineering. Aaron was awarded the 2010 Young Alumni Award from the University of Illinois for his achievements in the semiconductor industry. More recently, he received the Samsung R&D collaboration award for his technical leadership. In recognition of their work on Industry’s first 300mm III-V FinFETs, he and his team also received the 2014 Compound Semiconductor Industry R&D award. He has published over 100 papers in leading journals and conferences, and holds more than 50 technology US patents.  


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All are welcome to attend these Seminars. Should you have any enquiries, please contact Ms. Lily Png at 6516 6509 or you can e-mail to Ms Lily Png ().