||(1) Towards Next Generation Nanoelectronics Beyond Silicon CMOS; (2) P-N Junction Theory
|| Microelectronic Technologies & Devices
||Dr Ang Kah Wee, Institute of Microelectronics, A*STAR
||17 March 2014, Monday
||9:30 am to 12:00 pm
||E4-04-06, Engineering block E4, Faculty of Engineering, NUS
| (1) The continuous scaling of CMOS transistors has enabled extraordinary improvements in the switching speed, form-factor and cost of microprocessors. As CMOS scaling is pushed to its fundamental limit, the rising power dissipation has become a significant barrier to achieve system-level energy-efficiency. A reduction in power dissipation is therefore paramount to sustain the continuous increase in performance and circuit density. Much progress has been made in the past decades to manage power challenges. New electronic structure engineering using lattice-mismatched stressors at 90nm node and alternative gate dielectric/metal gate at 45nm node were used as performance booster when the supply voltage is scaled. The recent radical change in device architecture from a traditional planar structure to a 3-dimensional tri-gate transistor has enabled a drastic improvement in performance and electrostatic control at 22nm node. This led to a dramatic power reduction of gt;50% while achieving performance gain at low voltage.
To move beyond 10nm node where the supply voltage is expected to scale further, new channel materials (such as Ge, III-V and 2D materials) will be needed to modify the carrier transport properties significantly so as to keep up with the performance roadmap. These new channel materials are promising alternatives to silicon channel when work in tandem with the 3D device structure. Undoubtedly, future CMOS scaling will continue to be driven by innovations at all levels, including system architecture, circuit, device design, materials and process integration. This presentation will review the emerging research trends, challenges and opportunities to enable next generation of nanoelectronics beyond silicon CMOS.
(2) Understanding the basics of P-N junction is essential to understand transistor operation such as metal-oxide-semiconductor field-effect transistor (MOSFET). This lecture aims to provide the foundation for P-N junction formation and its electrostatic in thermal equilibrium such as the space charge density, the electric field, and the built-in potential. The lecture concludes with a qualitative discussion on the ideal I-V characteristics of a P-N junction diode.
The materials presented in this lecture are extracted from the following textbook:
Book: Semiconductor Device Fundamentals
Authors: Robert F. Pierret
|ABOUT THE SPEAKER|
| Kah-Wee ANG received his Bachelor in Electrical Engineering from Nanyang Technological University in 2002, Master of Science in Advanced Materials under the Singapore-MIT Alliance program in 2004, and Doctorate in Electrical Engineering from the National University of Singapore in 2008.
He was a manager for the non-planar CMOS scaling program at SEMATECH, USA, in 2010 where he led the team in developing advanced CMOS manufacturing technology for sub-10nm node and beyond. In 2012, he led the development of silicon photonics technology at GLOBALFOUNDRIES (Technology Development Department). He is currently with the Institute of Microelectronics, A*STAR. His current research interests are in nano-electronics and nano-photonics technologies. He has authored or co-authored ~100 journal and conference papers, including 23 invited papers/talks, and a book chapter. He received the IEEE Paul Rappaport Award in 2008 (Best Paper in IEEE Transactions on Electron Devices) and the Presidentís Technology Award in 2010.
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